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[SYNCHRON’12] Sequentially Constructive Concurrency: A Conservative Extension of the Synchronous Model of Computation. (slides)
M. Mendler.
Summary: Presentations of the [DATE’13] and [TECS’14] publications respectively.
Also presented at
- 19th International Workshop on Synchronous Programming (SYNCHRON'12), Le Croisic, France. November 2012
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- Electrical Engineering Research Seminar “PRETzel Forum” (PRETzel'14), Auckland University, New Zealand, January 2014.
Summary: Presentations of the [DATE’13] and [TECS’14] publications respectively.
[PDAY’13-1] Is timing analysis a refinement of causality analysis? (slides)
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PRET Day (PDAY'13), Inria Grenoble Rhône-Alpes France, , March 2013.
Summary: We ask this question by means of examples constructed from a game-theoretic approach for the semantics of Esterel combined with an interface algebra for timing analysis.
It has been recognised that the synchronous model of computation together with a suitable execution platform (precision-timed, or PRET architectures) facilitates system-level timing predictability. This talk discusses a logical and game-theoretic framework for capturing worst-case reaction time (WCRT) for Esterel-style synchronous reactive programming. This framework will provide a formal grounding for the WCRT problem, and allow to improving upon earlier heuristics by accurately and modularly characterising timing interfaces. This approach will not only allows verifying the correctness of WCRT analyses methods, but also will allow capturing functionality and timing together.
[PDAY’13-2] Constructive Boolean Networks and the Exactness of Timed Ternary Simulation. (slides)
[D-CON'13] Constructive Boolean Circuits and the Exactness of Timed Ternary Simulation.
[ECERS'14] Constructive Circuits and the Synchrony Hypothesis.
M. Mendler.
- PRET Day (PDAY'13), Inria Grenoble Rhône-Alpes France, March 2013.
- German Chapter Concur Meeting (D-CON'13), Institute for Software Engineering and Programming Languages, University of Lübeck, Germany, March 2013.
- Joint Electrical Engineering and Computer Science Departmental Seminar (ECERS'14), Auckland University, New Zealand, January 2014.
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Summary: Presentations of materials included in the [FMSD’12] publication.
M. Mendler.
Summary: Presentations of materials included in the [FMSD’12] publication.
Cyclic boolean systems, such as those arising in asynchronous circuits the semantics of synchronous programming languages, do not admit a unique canonical execution semantics. Instead, different approaches impose different restrictions on their stabilization behavior. This talk concerns This talk concerns the class of constructive circuits, for which signals settle to a unique value in bounded time, for any input, under a simple conservative delay model, called the up-bounded non-inertial (UN) delay. The main result is that ternary simulation decides the class of constructive circuits, for which signals settle to a unique value in bounded time, for any input, under a simple conservative delay model, called . It shows that three-valued algebra is able to maintain correct and exact stabilization information under the UN-delay model, which thus provides an adequate electrical interpretation of ternary algebra, which has been missing in the literature. Previous work on combinational circuits used the up-bounded non- inertial (UNUI) delay . The main result is that ternary simulation decides the class of constructive circuits. It shows that three-valued algebra is able to maintain correct and exact stabilization information under the UN-delay model, which thus provides an adequate electrical interpretation of ternary algebra, which has been missing in the literature. Previous work on combinational circuits used the up-bounded inertial (UI) delay to justify ternary simulation. It can be shown that the match is not exact and that stabilization under the UI-model, in general, cannot be decided by ternary simulation. As the corner-stone of our main results we introduce UN-Logic, an axiomatic specification language for UN-delay circuits that mediates between the real-time behavior and its abstract simulation in the ternary domain. We present a symbolic simulation calculus for circuit theories expressed in UN-logic and prove it sound and complete for the UN-model. This provides, for the first time, a correctness and exactness result for the timing analysis of cyclic circuits such as the timed extension of Malik's or Brzozowski and Seger's pure ternary algorithm or the timed algorithm proposed by Riedel and Bruck, which were not formally linked with real-time execution modelsto justify ternary simulation. It can be shown that the match is not exact and that stabilization under the UI-model, in general, cannot be decided by ternary simulation. As the corner-stone of our main results we introduce UN-Logic, an axiomatic specification language for UN-delay circuits that mediates between the real-time behavior and its abstract simulation in the ternary domain. We present a symbolic simulation calculus for circuit theories expressed in UN-logic and prove it sound and complete for the UN-model. This provides, for the first time, a correctness and exactness result for the timing analysis of cyclic circuits such as the timed extension of Malik's or Brzozowski and Seger's pure ternary algorithm or the timed algorithm proposed by Riedel and Bruck, which were not formally linked with real-time execution models.
Also presented at:
- [D-CON'13] Constructive Boolean Circuits and the Exactness of Timed Ternary Simulation.
German Chapter Concur 2013, Institute for Software Engineering and Programming Languages, University of Lübeck, Germany, March 2013. - [ECERS'14] Constructive Circuits and the Synchrony Hypothesis.
Joint Electrical Engineering and Computer Science Departmental Seminar, Auckland University, New Zealand, January 2014.
[PTCONF’13] SCCharts: Sequentially Constructive Charts. (poster)
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