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# Topics for Student Theses

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Version 40

Here's a selection of possible bachelor and master topics. If you're interested in one of them, don't hesitate to contact us! We'll sit down, have tea, and talk about what we great things we could do together.

# Graph Layout

Advisors: Ulf Rüegg, Christoph Daniel Schulze.

• Tight Packing of Connected Components (Bachelor)
Different connected components of a graph are often laid out separately and combined again afterwards. This combination step often produces too much whitespace. Research relevant 2D packing literature and implement a better solution.
KIPRA-1262 - Getting issue details... STATUS
KIPRA-1031 - Getting issue details... STATUS
• Integrate KIML with JGraph (Bachelor)
Provide automatic layout through KIML for the JGraph diagram library and develop a simple JGraph-based graph editor to test the integration with.
KIPRA-1214 - Getting issue details... STATUS
• Improved Edge Label Placement (Bachelor)
Our layout algorithm already supports the placement of edge labels. However, there's still room for improvement...
• Layering Algorithms (Bachelor, Master)
Implement an alternative algorithm for the layer assignment problem used in the layer-based approach to graph layout. The focus of the algorithm could the consideration of the number of edge crossings, a given aspect ratio, or overall compactness.
• Node Placement With a Focus on Compactness (Master)
Node placement algorithms often try to draw as many edges as straight lines as possible. However, that usually results in less compact diagrams. The focus of this topic would be to devise or adapt a node placement algorithm that tries to strike a balance between straightness and compactness.
• Compound Graph Layout (Master)
Design and implement new concepts for computing layer-based layouts of compound graphs. The main focus shall be on maintainability: ensuring that the implementation can be kept working over the years. The main area to be considered here is the crossing minimization phase.
• Force Based Drawing with Port Constraints (Master)
Develop methods for integrating port constraints in force-based drawing approaches. The resulting node placement shall be evaluated using an edge router such as libavoid on the model library of Ptolemy.
• Combining Forces and Layers (Master)
Design and implement a layout algorithm that combines the force-based and the layer-based approaches. The first three phases of the layer-based approach shall be replaced by a node distribution computed with a force-based approach.

# Modeling Pragmatics

Advisors: Reinhard von Hanxleden, Ulf Rüegg, Christoph Daniel Schulze.

• Comment Attachment (Bachelor)
When computing a new layout for a diagram that contains comments (comparable to comments in source code), the comments often get placed far away of the nodes they refer to. This is because often the reference is not explicitly encoded in the original model. We have used a distance-based metric in the past to discover references automatically, but there are lots of ideas for improvement. This bachelor thesis would implement them, perhaps come up with additional ideas, and finally evaluate them in a thorough experiment.
• Control Flow Graph Exploration / Visualization (Bachelor)
Use pragmatics concepts (automatic layout, focus & context) for exploring/visualizing control flow graphs and specific paths, eg. as computed by OTAWA WCET analysis tool, eg. using KLighD.
• Compound Graph Exploration (Bachelor, Master)
A new graph exploration approach should be examined which is uses different zoom levels for different compound nodes. This tries to map the "Google Maps approach" of only showing the information of interest at any given zoom level to the field of graph exploration.

# Semantics and Synchronous Languages

Advisors: Christian Motika, Steven Smyth.

• Validation Manager for Models
Develop an integrated, flexible and generic syntactic validation framework for models (e.g. Esterel or SyncCharts).
• SCCharts compiler validation with Esterel
Automate the validation of the SCCharts compiler using the Esterel simulation.
• Transformation from SCCharts to Esterel [possibly also Master Topic]
Develop a transformation in Xtend2 to generate Esterel code for SCCharts.
• Hardware Synthesis from SCCharts to FPGA [possibly also Master Topic]
Use the circuit-based code generation to produce code for FPGAs
• Automatic documentation generation [possibly also Master Topic]
Develop an automatic SCCharts documentation system
• Optimizations for the SCCharts compiler [possibly also Master Topic]
Profile the actual SCCharts compiler and apply optimizations
• Multi-core SCCharts compiler [possibly also Master Topic]
Implement the possibility to use more than one core to compile large SCCharts
• Adding dataflow to SCCharts [possibly also Master Topic]
Add dataflow to SCCharts

# PRETSY / PRETSY2

• Real-time extensions for SCCharts [possibly also Master Topic]
Make the timing instructions delay_until und exception_on_expire of the FlexPRET processor available in SCCharts.
• See also Semantics and Synchronous Languages: Adding dataflow to SCCharts

# Miscellaneous Topics

Advisors: to be determined.

• Developing an Info Screen (Bachelor)
Info screens are screens that present data in ways that can be easily understood. This includes static data (project description graphics, members of a team, ...) as well as dynamically aggregated data (bug statistics, automatic build overviews, ...). This topic is about developing such an info screen for our group and making it easily configurable.

# Master Topics

## Semantics and Synchronous Languages

• Quartz
Integrate the synchronous Quartz language into KIELER for validation purposes and teaching.
• Implementation of a priority-based compilation approach
Implement the SyncCharts priority-based compilation approach into the SCCharts compiler chain.
• Curing Schizophrenia in SCCharts
Develop new synchronizer to handle schizophrenia properly (e.g. depth join).
• Detecting tick boundaries in SCCharts
Implement an algorithm that detects tick boundaries (in concurrent) threads and therefore improves the scheduling
• Multithreaded/Multicore execution of SCCharts (see below PRETSY/PRETSY2)
• Railway 2.0
Design a new and modern hardware controlling (Version 4) for the railway installation.

## PRETSY / PRETSY2

• Multithreaded/Multicore execution of SCCharts
Evaluate possibilities to preserve parallelism in SCCharts, implement mapping for (fine grained) multithreading and multicore
based on the FlexPRET processor.

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