PRETSY - Precision-Timed Synchronous Reactive Processing
The PRETSY project is a project funded by the German Research Foundation (DFG HA 4407/6-1), running 2011 - 2014.
Embedded reactive real-time systems are ubiquitous today, and provide increasingly complex functionality for example in modern automotive, avionics or medical products. This rising complexity makes it important to apply high-level design approaches, which, however, traditionally make critical low-level aspects such as timing hard to control. This project will investigate a novel, holistic approach for the design of timing-predictable, efficient reactive systems, which considers the modeling and programming level as well as the execution platform.
A key contribution will be to combine a formal semantical basis, which is provided by the synchronous model of computation and which results in predictable reactive control flow, with recent architectural developments that offer predictable timing at the instruction level. Compared to typical design approaches today, based on C-like languages and processors that optimize the average case at the expense of predictability, this will reduce timing uncertainties at the control-flow level as well as the architectural level. On the practical side the project will develop a model-based design flow and tool chain for implementing timing-predictable, reactive systems, including a synchronous modeling and programming language, a compiler, a timing analyzer, and a predictable execution platform derived from the Berkeley/Columbia PRET architecture.
Reinhard v. Hanxleden, Kiel University
Michael Mendler, Bamberg University
Stephen Edwards, Columbia University
Alain Girault, INRIA Grenoble
Edward Lee, UC Berkeley
Gerald Lüttgen, Bamberg University
Marc Pouzet, ENS Paris
Partha Roop, University of Auckland
Zoran Salcic, University of Auckland
Reinhard Wilhelm, Saarland University