The testbench is a VHDL file which is used by ISE Simulator to test a VHDL component.
ISE is a programming an simulation tool to develop XILINX FPGAs. This work suite include a programminng workspace, a compiler, simulator (ISIM) and much more.
When you program a new component, you also want to test its behavior. But you do not always have an FPGA, so you could use a simulator. For that the simulator knows what input signals to simulate you need a so called tesbench.
A testbench lists the component you want to test e.g. abo. (You have written a vhdl file which behaves like ABO and this component is also called abo). It instantiate this componant as a Unit Under Test (UUT). This component (uut) will be tested with the input and outputs you have specified in a test process.
At first a testbench code example from ABO is shown for better understanding.
--/*****************************************************************************/ --/* G E N E R A T E D V H D L C O D E */ --/*****************************************************************************/ --/* KIELER - Kiel Integrated Environment for Layout Eclipse RichClient */ --/* */ --/* http://www.informatik.uni-kiel.de/rtsys/kieler/ */ --/* Copyright 2013 by */ --/* + Christian-Albrechts-University of Kiel */ --/* + Department of Computer Science */ --/* + Real-Time and Embedded Systems Group */ --/* */ --/* This code is provided under the terms of the Eclipse Public License (EPL).*/ --/*****************************************************************************/ LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY abo_tb IS END abo_tb; ARCHITECTURE behavior OF abo_tb IS COMPONENT abo PORT( tick : IN std_logic; reset : IN std_logic; --inputs A: IN boolean; B: IN boolean; --outputs O1 : OUT boolean; O2 : OUT boolean; A_out : OUT boolean; B_out : OUT boolean ); END COMPONENT; --Inputs signal A : boolean := false; signal B : boolean := false; --Outputs signal O1 : boolean := false; signal O2 : boolean := false; signal A_out : boolean := false; signal B_out : boolean := false; --Control signal reset : std_logic := '0'; signal tick : std_logic := '0'; constant tick_period : time := 100 ns; BEGIN uut: abo PORT MAP( tick => tick, reset => reset, --Inputs A => A, B => B, --Outputs O1 => O1, O2 => O2, A_out => A_out, B_out => B_out ); tick_process: process begin tick <= '0'; wait for tick_period/2; tick <= '1'; wait for tick_period/2; end process; -- Stimulus process stim_proc: process begin wait for 1 ps; --sim Process --NEW TRACE reset <= '1'; wait for tick_period; reset <= '0'; -- tick 1 A <= true; B <= false; wait for tick_period; assert( O1 = true ) report "1st trace: 1st tick: O1 should have been true" severity ERROR; assert( O2 = false ) report "1st trace: 1st tick: O2 should have been false" severity ERROR; assert( A_out = true ) report "1st trace: 1st tick: A_out should have been true" severity ERROR; assert( B_out = true ) report "1st trace: 1st tick: B_out should have been true" severity ERROR; -- tick 2 A <= false; B <= false; wait for tick_period; assert( O1 = true ) report "1st trace: 2nd tick: O1 should have been true" severity ERROR; assert( O2 = false ) report "1st trace: 2nd tick: O2 should have been false" severity ERROR; assert( A_out = false ) report "1st trace: 2nd tick: A_out should have been false" severity ERROR; assert( B_out = false ) report "1st trace: 2nd tick: B_out should have been false" severity ERROR; -- tick 3 A <= false; B <= true; wait for tick_period; assert( O1 = false ) report "1st trace: 3rd tick: O1 should have been false" severity ERROR; assert( O2 = true ) report "1st trace: 3rd tick: O2 should have been true" severity ERROR; assert( A_out = false ) report "1st trace: 3rd tick: A_out should have been false" severity ERROR; assert( B_out = true ) report "1st trace: 3rd tick: B_out should have been true" severity ERROR; --NEW TRACE reset <= '1'; wait for tick_period; reset <= '0'; -- tick 1 A <= false; B <= false; wait for tick_period; assert( O1 = false ) report "2nd trace: 1st tick: O1 should have been false" severity ERROR; assert( O2 = false ) report "2nd trace: 1st tick: O2 should have been false" severity ERROR; assert( A_out = false ) report "2nd trace: 1st tick: A_out should have been false" severity ERROR; assert( B_out = false ) report "2nd trace: 1st tick: B_out should have been false" severity ERROR; -- tick 2 A <= true; B <= false; wait for tick_period; assert( O1 = false ) report "2nd trace: 2nd tick: O1 should have been false" severity ERROR; assert( O2 = true ) report "2nd trace: 2nd tick: O2 should have been true" severity ERROR; assert( A_out = true ) report "2nd trace: 2nd tick: A_out should have been true" severity ERROR; assert( B_out = true ) report "2nd trace: 2nd tick: B_out should have been true" severity ERROR; wait; end process; END; |
Line 23: ABO component declaration
Here the ABO component is declared, so the testbanch knows which component to test.
Line 38: declaration of local signals
Local signals are needed for internal communication and for interconnection between components and processes.
Line 55: instantiation of uut
Here is ABO instantiated
Line 69: tick process
The tick process simulates the tick. This signal is a kind of a clock signal. Its cycle duration is set in variable tick_period.
Line 79: the simulation process
The main simulation process, here the input signals are set and the output signals are tested according to specifications in ESO file.
Therefore the core ESO contains no information about input and output signals the proper SCL model is needed to generate the testbench.
The variable declaration must conform to the used variables in the ESO file, logically.
SCL Model | Core ESO File | ESO File | |||
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SCL file is not realy correct, will be corrected as soon as possible |
The lines 23 to 66 (testbench file) were generated from the SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is needed for code generation.
The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be shown at the following example:
SCL | ESO trace | Testbench | |||
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normally the core ESO is used, but for better unterstanding we use the normal ESO trace
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Set inputs
Line 2 and 3 in the testbench are setting the inputs. All (!) inputs must be set!
Wait for the tick to pass by
The code wait for tick_period; waits for one tick, so the Hardware can compute the output values.
Test Outputs
After the tick has passed by we must check if the hardware computes the correct outputs. This is done by assertions. Every (!) output must be tested!
If an assertion failed the corresponding error will be printed to a log file. The severity level tells the simulator to go on with the simulation although an error occur.