PRETSY - Precision-Timed Synchronous Reactive Processing

The PRETSY project is a project funded by the German Research Foundation (DFG HA 4407/6-1), running 2011 - 2014.


Embedded reactive real-time systems are ubiquitous today, and provide increasingly complex functionality for example in modern automotive, avionics or medical products. This rising complexity makes it important to apply high-level design approaches, which, however, traditionally make critical low-level aspects such as timing hard to control. This project will investigate a novel, holistic approach for the design of timing-predictable, efficient reactive systems, which considers the modeling and programming level as well as the execution platform.

A key contribution will be to combine a formal semantical basis, which is provided by the synchronous model of computation and which results in predictable reactive control flow, with recent architectural developments that offer predictable timing at the instruction level. Compared to typical design approaches today, based on C-like languages and processors that optimize the average case at the expense of predictability, this will reduce timing uncertainties at the control-flow level as well as the architectural level. On the practical side the project will develop a model-based design flow and tool chain for implementing timing-predictable, reactive systems, including a synchronous modeling and programming language, a compiler, a timing analyzer, and a predictable execution platform derived from the Berkeley/Columbia PRET architecture.


Reinhard v. Hanxleden, Kiel University

Michael Mendler, Bamberg University

Collaborating Scientists:

Stephen Edwards, Columbia University

Alain Girault, INRIA Grenoble

Edward Lee, UC Berkeley

Gerald Lüttgen, Bamberg University

Marc Pouzet, ENS Paris

Partha Roop, University of Auckland

Zoran Salcic, University of Auckland

Reinhard Wilhelm, Saarland University

Internal Documents:

Internal Documents


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Sequentially Constructive Concurrency: A Conservative Extension of the Synchronous Model of Computation.

R. von Hanxleden, M. Mendler, J. Aguado, B. Duderstadt, I. Fuhrmann, C. Motika, S. Mercer, O. O'Brian

Design, Automation Test in Europe Conference (DATE’13), March 2013: 581-586.

Abstract. Synchronous languages ensure deterministic concurrency, but at the price of heavy restrictions on what programs are considered valid, or constructive. Meanwhile, sequential languages such as C and Java offer an intuitive, familiar programming paradigm but provide no guarantees with regard to deterministic concurrency. The sequentially constructive (SC) model of computation (MoC) presented here harnesses the synchronous execution model to achieve deterministic concurrency while addressing concerns that synchronous languages are unnecessarily restrictive and difficult to adopt.

In essence, the SC MoC extends the classical synchronous MoC by allowing variables to be read and written in any order as long as sequentiality expressed in the program provides sufficient scheduling information to rule out race conditions. This allows to use programming patterns familiar from sequential programming, such as testing and later setting the value of a variable, which are forbidden in the standard synchronous MoC. The SC MoC is a conservative extension in that programs considered constructive in the common synchronous MoC are also SC and retain the same semantics. In this paper, we investigate classes of shared variable accesses, define SC admissible scheduling as a restriction of "free scheduling," derive the concept of sequential constructiveness, and present a priority-based scheduling algorithm for analyzing and compiling SC programs efficiently.


A Game Semantics for Instantaneous Esterel Reactions.

J. Aguado

CSI Journal of Computing. Vol.2, No.1-2, e-ISSN 2277-7091, 2013: 30-44.

Abstract. The present paper explains the constructive semantics of the synchronous language Estterel in terms of winning strategies in finite two–player games. The kernel fragment of Esterel considered here corresponds to combinational circuits and includes the statements for signal emission, status test, parallel composition and gives for the first time a game–theoretic interpretation to sequential composition and local signal declaration. This modelling shows how non-classical truth values induced by logic games can be used to characterise the constructive single-step semantics for Esterel.




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