Slot	Processor
Before phase 1	Compound Cycle Processor Graph Transformer Comment Preprocessor Edge And Layer Constraint Edge Reverser
Before phase 2	Big Nodes Processor Label Dummy Inserter
Before phase 3	Layer Constraint Processor Hierarchical Port Constraint Processor Compound Dummy Edge Remover Long Edge Splitter Port Side Processor Label Dummy Switcher Inverted Port Processor Self Loop Processor Port List Sorter North South Port Preprocessor
Before phase 4	Subgraph Ordering Processor In Layer Constraint Processor Hyperedge Dummy Merger Label Side Selector Label And Node Size Processor Port Position Processor Node Margin Calculator Compound Side Processor
Before phase 5	Hierarchical Port Dummy Size Processor Hierarchical Port Position Processor
After phase 5	Comment Postprocessor Hypernode Processor Hierarchical Port Orthogonal Edge Router Long Edge Joiner North South Port Postprocessor Label Dummy Remover Reversed Edge Restorer Compound Graph Restorer Graph Transformer End Label Processor

Preconditions	The graph is layered.
Postconditions	Odd port side dummy nodes are inserted for odd ports. The graph may contain new in-layer connections.
Slot	Before phase 3.
Dependencies	`PortSideProcessor`
Remarks	The following phases must support in-layer connections for this to work.

Label And Node Size Processor

Calculates node sizes, places ports, and places node and port labels.

Preconditions	The graph is layered. Crossing minimization is finished. Port constraints are at least at `FIXED_ORDER`. Port lists are properly sorted going clockwise, starting at the leftmost northern port.
Postconditions	Port positions are fixed. Port labels are placed. Node labels are placed. Node sizes are set.
Slot	Before phase 4.
Dependencies	`LabelSideSelector`
Remarks	Replaces the old `PortPositionProcessor`.

Label Dummy Inserter

TODO: Document.

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