Slot	Processor	Tested
Before phase 1	Compound Cycle Processor Graph Transformer Comment Preprocessor Edge And Layer Constraint Edge Reverser
Before phase 2	Big Nodes Processor Label Dummy Inserter
Before phase 3	Layer Constraint Processor Hierarchical Port Constraint Processor Compound Dummy Edge Remover Long Edge Splitter Port Side Processor Label Dummy Switcher Inverted Port Processor Self Loop Processor Port List Sorter North South Port Preprocessor
Before phase 4	Subgraph Ordering Processor In Layer Constraint Processor Hyperedge Dummy Merger Label Side Selector Label And Node Size Processor Node Margin Calculator Compound Side Processor
Before phase 5	Layer Size and Graph Height Calculator Hierarchical Port Dummy Size Processor Hierarchical Port Position Processor
After phase 5	Comment Postprocessor Hypernode Processor Hierarchical Port Orthogonal Edge Router Long Edge Joiner North South Port Postprocessor Label Dummy Remover Reversed Edge Restorer Compound Graph Restorer Graph Transformer End Label Processor

Preconditions	The graph is layered.
Postconditions	All nodes have at least fixed port sides.
Slot	Before phase 3.
Dependencies	None.
Remarks	None.
Tests	No node has its PortConstraints set to FREE or UNDEFINED Every port has a specified PortSide.

Reversed Edge Restorer

Restores the direction of reversed edges.

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