Slot	Processor	Tested
Before phase 1	Compound Cycle Processor Graph Transformer Comment Preprocessor Edge And Layer Constraint Edge Reverser
Before phase 2	Big Nodes Processor Label Dummy Inserter
Before phase 3	Layer Constraint Processor Hierarchical Port Constraint Processor Compound Dummy Edge Remover Long Edge Splitter Port Side Processor Label Dummy Switcher Inverted Port Processor Self Loop Processor Port List Sorter North South Port Preprocessor
Before phase 4	Subgraph Ordering Processor In Layer Constraint Processor Hyperedge Dummy Merger Label Side Selector Label And Node Size Processor Node Margin Calculator Compound Side Processor
Before phase 5	Layer Size and Graph Height Calculator Hierarchical Port Dummy Size Processor Hierarchical Port Position Processor
After phase 5	Comment Postprocessor Hypernode Processor Hierarchical Port Orthogonal Edge Router Long Edge Joiner North South Port Postprocessor Label Dummy Remover Reversed Edge Restorer Compound Graph Restorer Graph Transformer End Label Processor

Preconditions	The graph is layered.
Postconditions	Odd port side dummy nodes are inserted for odd ports. The graph may contain new in-layer connections.
Slot	Before phase 3.
Dependencies	`PortSideProcessor`
Remarks	The following phases must support in-layer connections for this to work.
Tests	Westwards outgoing edges have to target a dummy node in the same layer. Analog: Eastwards incoming edges.

Label And Node Size Processor

...

Preconditions	The graph is layered.
Postconditions	The graph is properly layered.
Slot	Before phase 3.
Dependencies	`LayerConstraintProcessor`
Remarks	None.
Tests	All edges connect directly adjacent layers with an increasing index.

Node Margin Calculator

Calculates node margins based on port positions and sizes and label positions and sizes.

...