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...

Code Block

linenumbers	true


--/*****************************************************************************/
--/*               G E N E R A T E D     V H D L    C O D E                    */
--/*****************************************************************************/
--/* KIELER - Kiel Integrated Environment for Layout Eclipse RichClient        */
--/*                                                                           */
--/* http://www.informatik.uni-kiel.de/rtsys/kieler/                           */
--/* Copyright 2013 by                                                         */
--/* + Christian-Albrechts-University of Kiel                                  */
--/*   + Department of Computer Science                                        */
--/*     + Real-Time and Embedded Systems Group                                */
--/*                                                                           */
--/* This code is provided under the terms of the Eclipse Public License (EPL).*/
--/*****************************************************************************/

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY abo_tb IS    
END abo_tb;

ARCHITECTURE behavior OF abo_tb IS

COMPONENT abo
PORT(
     tick : IN  std_logic;
     reset : IN std_logic;
     --inputs
     A: IN boolean;
     B: IN boolean;
     --outputs
     O1 : OUT boolean;
     O2 : OUT boolean;
     A_out : OUT boolean;
     B_out : OUT boolean
    );
END COMPONENT;

--Inputs
signal A : boolean := false;
signal B : boolean := false;

--Outputs
signal O1 : boolean := false;
signal O2 : boolean := false;
signal A_out : boolean := false;
signal B_out : boolean := false;

--Control
signal reset : std_logic := '0';
signal tick : std_logic := '0';
constant tick_period : time := 100 ns;

BEGIN
    
    uut: abo PORT MAP(
        tick => tick,
        reset => reset,
        --Inputs
        A => A,
        B => B,
        --Outputs
        O1 => O1,
        O2 => O2,
        A_out => A_out,
        B_out => B_out
    );
    
    
    tick_process: process
    begin
        tick <= '0';
        wait for tick_period/2;
        tick <= '1';
        wait for tick_period/2;
    end process;

    
    -- Stimulus process
    stim_proc: process
    begin        
        wait for 1 ps;
        
        --sim Process
        
        
        --NEW TRACE
        reset <= '1';
        wait for tick_period;
        reset <= '0';
        
        -- tick 1
        A <= true;
        B <= false;
        wait for tick_period;
        assert( O1 = true )
            report "1st trace: 1st tick: O1 should have been true"
            severity ERROR;
        assert( O2 = false )
            report "1st trace: 1st tick: O2 should have been false"
            severity ERROR;
        assert( A_out = true )
            report "1st trace: 1st tick: A_out should have been true"
            severity ERROR;
        assert( B_out = true )
            report "1st trace: 1st tick: B_out should have been true"
            severity ERROR;
        
        -- tick 2
        A <= false;
        B <= false;
        wait for tick_period;
        assert( O1 = true )
            report "1st trace: 2nd tick: O1 should have been true"
            severity ERROR;
        assert( O2 = false )
            report "1st trace: 2nd tick: O2 should have been false"
            severity ERROR;
        assert( A_out = false )
            report "1st trace: 2nd tick: A_out should have been false"
            severity ERROR;
        assert( B_out = false )
            report "1st trace: 2nd tick: B_out should have been false"
            severity ERROR;
        
        -- tick 3
        A <= false;
        B <= true;
        wait for tick_period;
        assert( O1 = false )
            report "1st trace: 3rd tick: O1 should have been false"
            severity ERROR;
        assert( O2 = true )
            report "1st trace: 3rd tick: O2 should have been true"
            severity ERROR;
        assert( A_out = false )
            report "1st trace: 3rd tick: A_out should have been false"
            severity ERROR;
        assert( B_out = true )
            report "1st trace: 3rd tick: B_out should have been true"
            severity ERROR;
        
        --NEW TRACE
        reset <= '1';
        wait for tick_period;
        reset <= '0';
        
        -- tick 1
        A <= false;
        B <= false;
        wait for tick_period;
        assert( O1 = false )
            report "2nd trace: 1st tick: O1 should have been false"
            severity ERROR;
        assert( O2 = false )
            report "2nd trace: 1st tick: O2 should have been false"
            severity ERROR;
        assert( A_out = false )
            report "2nd trace: 1st tick: A_out should have been false"
            severity ERROR;
        assert( B_out = false )
            report "2nd trace: 1st tick: B_out should have been false"
            severity ERROR;
        
        -- tick 2
        A <= true;
        B <= false;
        wait for tick_period;
        assert( O1 = false )
            report "2nd trace: 2nd tick: O1 should have been false"
            severity ERROR;
        assert( O2 = true )
            report "2nd trace: 2nd tick: O2 should have been true"
            severity ERROR;
        assert( A_out = true )
            report "2nd trace: 2nd tick: A_out should have been true"
            severity ERROR;
        assert( B_out = true )
            report "2nd trace: 2nd tick: B_out should have been true"
            severity ERROR;
        wait;
    end process;

END;

...

The variable declaration must fit to the used variables in the ESO file, logically.

SCL Model

Core ESO fileFile

ESO File

Code Block

language	java
linenumbers	true

module ABO
input A : boolean;
input B : boolean;
output O1 : boolean = false;
output O2 : boolean = false;
output A_out : boolean;
output B_out : boolean;
{
    fork
        __WaitAB_HandleA_WaitA:
        if A then
            A_out = true;
            B = true;
            B_out = true;
            O1 = true;
            goto __WaitAB_HandleA_DoneA;
        end;
        pause;
        goto __WaitAB_HandleA_WaitA;
        __WaitAB_HandleA_DoneA:
    par
        __WaitAB_HandleB_WaitB:
        pause;
        if ! B then
            goto __WaitAB_HandleB_WaitB;
        end;
        B_out = true;
        O1 = true;
    join;
    O1 = false;
    O2 = true;
}

Code Block

language	perl
linenumbers	true

!reset ;
%% A : true 
%% O1 : true 
%% A_out : true 
%% B_out : true 
;

%% O1 : true 
;

%% B : true 
%% O2 : true 
%% B_out : true 
;

!reset ;
;

%% A : true 
%% O2 : true 
%% A_out : true 
%% B_out : true 
;

Note
SCL file is not realy correct, will be corrected as soon as possible

The lines 23 to 66 (testbench file) are generated from SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is loaded and the needed code is generated.

...

Code Block

language	perl
linenumbers	true

!reset ;
A
% Output : O1 A_out B_out 
;
% Output : O1
;
B 
% Output : O2 B_out
;
!reset ;
% Output : 
;
A
% Output : O2 A_out B_out
;

Note
SCL file is not realy correct, will be corrected as soon as possible

The lines 23 to 66 (testbench file) are generated from SCL model file. The model tells the transformation which input and output the abo component must have and the type of these variables (signals in VHDL). So the SCl file is loaded and the needed code is generated.

The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be schown at the follwing example:

ESO trace

Testbench

Code Block

language	perl
linenumbers	true

!reset;
A B(5) C(false)
%Output: D E(3) F(false)
;

normally the core ESO is used, but

for better unterstanding we use the

normal ESO trace

Code Block

language	java
linenumbers	true

A <= true;
B <= false;
C <= true;
C_value <= false;
wait for tick_period;
assert( D = true )
	report "1st trace: 1st tick: D should have been true"
	severity ERROR;
assert( E = false )
	report "1st trace: 1st tick: E should have been false"
	severity ERROR;
assert( F = true )
	report "1st trace: 1st tick: F should have been true"
	severity ERROR;
assert( F_value = false )
	report "1st trace: 1st tick: F_value should have been false"
	severity ERROR;

Line 2 and 3 in the testbench are setting the inpute. All (!) inputs must be set! Signal which are present are set to the according value

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