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The simulation process (starts at line 79) is generated using the core ESO file. How the simulation process is generated will be schown at the follwing example:

module test
input  A ;

input  B

A <= true;
B <= false;
C <= true;
C_value <= false;
wait for tick_period;
assert( D = true )
	report "1st trace: 1st tick: D should have been true"
	severity ERROR;
assert( E = false )
	report "1st trace: 1st tick: E should have been false"
	severity ERROR;
assert( F = true )
	report "1st trace: 1st tick: F should have been true"
	severity ERROR;
assert( F_value = false )
	report "1st trace: 1st tick: F_value should have been false"
	severity ERROR;

Line 2 and 3 in the testbench are setting the inpute. All (!) inputs must be set! Signal which are present are set to the according value

...

 : boolean = false;
input  B_value : integer = 0;
input  C :boolean = false;
input  C_value :boolean = false;
output  D;
output  E : boolean = false;
output  E_value : integer = 5;
output  F : boolean = false;
output  F_value : boolean = false;
{
    //pause;    
}

!reset;
A C(false)
%Output: D F(false)
;

A <= true;
B <= false;
C <= true;
C_value <= false;
wait for tick_period;
assert( D = true )
	report "1st trace: 1st tick: D should have been true"
	severity ERROR;
assert( E = false )
	report "1st trace: 1st tick: E should have been false"
	severity ERROR;
assert( F = true )
	report "1st trace: 1st tick: F should have been true"
	severity ERROR;
assert( F_value = false )
	report "1st trace: 1st tick: F_value should have been false"
	severity ERROR;

Set inputs

Line 2 and 3 in the testbench are setting the inpute. All (!) inputs must be set!

• Pure signal which are present are set to the according value, e.g. A<=true;
• Valued signals which are present are set to thier according value e.g. C_value <= false; and set present B<=true;
• ABSENT values (not listed in ESO files inputs) mus be set absent
  • pure singals (not listeg) e.g. K <= false
  • valued signals e.g. B <= false, only the present value will be set, the valued signal is not touched

Wait for the tick to pass by

The code wait for tick_period; waits for one tick, so the Hardware can compute the output values.

Test Outputs

After the tick has passed by we must check if the hardware computes the correct outputs. This is done by assertions. Every (!) output must tested!

• Pure signals: Test the pure output signal according to the current ESO tick, if listed, e.g. assert( D = true ). If it is not specified in the trace test for absence,
• Valued signals: For valued signals that are specified in the current ESO tick test the present singal and the valued signal, e.g. assert( F = true ) and assert( F_value = false)
• Valued signals which are not listed in the current tick in the ESO file: test only the present flag for absence (We cannot say anything about absent valued signals)

If an assertion failed the corresponding error will be printed to a log file. The severity level tells the simulator to go on with the simulation altough an error acoored.