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Heinzcmann, C., & Lange, R. vTSL-A Formally Verifiable DSL for Specifying Robot Tasks. In 2018 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)

Hyunuk Jung, Kangnyoung Lee, and Soonhoi Ha. 2000. Efficient hardware controller synthesis for synchronous dataflow graph in system level design. In Proceedings of the 13th international symposium on System synthesis (ISSS '00)

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Srinivas Pinisetty, Partha S. Roop, Steven Smyth, Stavros Tripakis and Reinhard von Hanxleden. Runtime enforcement of reactive systems using synchronous enforcers. In CoRR, vol. abs/1612.05030, 2016.

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