| Slot | Processor | Tested |
|---|
| Before phase 1 | Graph Transformer
Comment Preprocessor
Edge And Layer Constraint Edge Reverser | 
 |
| Before phase 2 | Big Nodes Processor
Label Dummy Inserter | | |
| Before phase 3 | Layer Constraint Processor
Hierarchical Port Constraint Processor
Long Edge Splitter
Port Side Processor
Label Dummy Switcher
Inverted Port Processor
Self Loop Processor
Port List Sorter
North South Port Preprocessor |
|
| Before phase 4 | In Layer Constraint Processor
Hierarchical Port Dummy Size Processor
Hyperedge Dummy Merger
Label Side Selector
Label And Node Size Processor
Node Margin Calculator |
|
| Before phase 5 | Layer Size and Graph Height Calculator
Hierarchical Port Position Processor |
|
| After phase 5 | Comment Postprocessor
Hypernode Processor
Hierarchical Port Orthogonal Edge Router
Long Edge Joiner
North South Port Postprocessor
Label Dummy Remover
Reversed Edge Restorer
Graph Transformer
End Label Processor |
|
